The present invention relates to integrated logic circuits with complementary MOS transistors and more particularly to bistable D flip-flop structures. A typical structure of the type concerned comprises at least three logic gates each formed by a first group of transistors of a first conduction type and a second group of transistors of a second conduction type, these two groups of transistors being connected in series across the terminals of a voltage supply source and their common connection point forming the output node of the gate. The conduction paths of the transistors are connected in series and/or in parallel within each group so that the conduction state of these transistors determines the potential at the output node of the gate, which potential represents the inner variable provided by this gate and may take values substantially equal to those at the two terminals of the supply voltage source, the terminal connected to the first group of transistors being at a potential 1 and that connected to the second group of transistors being at the potential 0. Each transistor is controlled either by an inner variable or by an external control variable such as D or H, H being a clock signal.
Such a structure may have a dynamic, semi-dynamic or static behaviour as far as the clock signal H is concerned. Various bistable D flip-flop structures are already known, in particular in the form of "master-slave" circuits, of circuits employing transmission gates and circuits obtained by so called "clocked circuit" techniques. A "master-slave" type circuit is disclosed for example in the U.S. Pat. No. 3,267,295. This circuit is intensitive to parasitic noise which might affect the control variable D and involves no logical hazards. This circuit however is relatively complicated because it comprises twenty-six MOS transistors. A circuit of this type is also disclosed in the catalogue of Solid State Scientific Inc., in a form allowing the same to be set to "one" and to "zero" and it comprises thirty-eight MOS transistors.
A circuit including transmission gates is described for example in the catalogue of National Semi-Conductor Corporation (circuit MM 74 C 74 Dual D Flip-Flop). This circuit is insensitive to parasitic noise affecting the control variable D. However, this circuit requires the presence of the clock variable in the true form (H) and in the inverted form (H), which constitutes a drawback from the point of view of the required surface of the integrated structure. Moreover, this circuit involves a logical hazard due to the delay of H with respect to H, the variables H and H being able to momentarily take the same value and to short-circuit two nodes having different logic states. It is thus necessary to control the delay of H with respect to H to obtain correct operation. Furthermore, the production of these structures in integrated form has a number of drawbacks due to bad separation of p- and n-channel transistors of the transmission gates used in this circuit.
Circuits referred to as "clocked circuits", are also known for example in the form of a dynamic circuit described in the Swiss Pat. No. 552914, in the form of a semi-dynamic circuit as disclosed by the article "Clocked CMOS Calculator Circuit" by YASOJI SUZUKI et al., in "IEEE Journal of Solid-State Circuits, Vol. SC-8, No. 6, December 1973, page 462," or in the form of a static circuit as disclosed in the French patent application published under the No. 2102186. These circuits have a behaviour which is insensitive to parasitic noise affecting the control variable D. They require the presence of a clock variable in the true form (H) and in the inverted form (H) with the disadvantage already mentioned above. Furthermore, these circuits have a logical hazard due to the delay of H with respect to H. Dynamic and semi-dynamic D flip-flop structures have further been described in the German patent application No. 25 41 255. In its dynamic version such a structure can be exempt from logical hazards. However, if the structure is simple (i.e. it includes 10 MOS transistors) it is sensitive to parasitic noise affecting the control variable D. If it is insensitive to those parasitic noise the dynamic structure needs 12 MOS transistors and is thus relatively complex. In its semi-dynamic form the structure described in the said prior patent application needs also a relatively large number of transistors.